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| MC74F299 8-INPUT UNIVERSAL SHIFT/STORAGE REGISTER WITH COMMON PARALLEL I/O PINS The MC74F299 is an 8-Bit Universal Shift/Storage Register with 3-state outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register. 8-INPUT UNIVERSAL SHIFT/STORAGE REGISTER WITH COMMON PARALLEL I/O PINS FASTTM SCHOTTKY TTL * Common I/O for Reduced Pin Count * Four Operation Modes: Shift left, Shift Right, Load and Store * Separate Shift Right Serial Input and Shift Left Serial Input for Easy Cascading * 3-State Outputs for Bus Oriented Applications * Input Clamp Diodes Limit High-Speed Termination Effects 20 1 J SUFFIX CERAMIC CASE 732-03 CONNECTION DIAGRAM V CC 20 S 1 19 DS 7 18 Q 7 17 I/O 7 16 I/O 5 15 I/O 3 14 I/O 1 13 CP DS 0 11 12 20 1 N SUFFIX PLASTIC CASE 738-03 20 1 1 S 0 2 OE 1 3 OE 2 4 I/O 6 5 I/O 4 6 I/O 2 7 I/O 0 8 Q 0 9 MR 10 GND DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 74 74 74 74 Min 4.5 0 Typ 5.0 25 Max 5.5 70 -1.0/- 3.0 20/24 Unit V C mA mA FAST AND LS TTL DATA 4-242 MC74F299 FUNCTION TABLE Inputs MR L H H H H S1 X H L H L S0 X H H L L CP X X Response Asynchronous Reset: Q0-Q7 = LOW Parallel Load: I/On Qn Shift Right: DS0 Q0, Q0 Q1, etc. Shift Left: DS7 Q7, Q7 Q6, etc. Hold H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH clock transition. FUNCTIONAL DESCRIPTION The MC74F299 is an 8-bit universal shift/storage register with 3-state outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. A separate active-LOW Master Reset is used to reset the register. The MC74F299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-state buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended set-up and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-state buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Q0/Q7 VOH Output HIGH Voltage I/O VOL Output LOW Voltage 74 74 74 74 Q0/Q7 I/O Q0/Q7 IIH Input HIGH Current I/O Q0/Q7 I/O IIL IOZH IOZL IOS ICC Input LOW Current Off-State Output Current, High-Level Voltage Applied Off-State Output Current, Low-Level Voltage Applied Output Short Circuit Current (Note 2) Total Supply Current - 60 S0, S1 Other Inputs 2.5 2.7 2.7 2.4 0.5 0.5 20 70 0.1 1.0 -1.2 - 0.6 70 1.0 - 0.6 -150 95 3.4 Min 2.0 0.8 -1.2 Typ Max Unit V V V V V V A mA mA A mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN, IIN = -18 mA VCC = 4.5 V IOH = -1.0 mA VCC = 4.75 V IOH = - 3.0 mA IOL = 20 mA IOL = 24 mA VCC = 4.75 V VCC = 4.5 V VCC = MIN VCC = MAX, VIN = 2.7 V VCC = MAX VIN = 7.0 V VIN = 5.5 V VCC = MAX, VIN = 0.5 V VCC = MAX VOUT = 2.7 V VOUT = 5.5 V VCC = MAX, VOUT = 0.5 V VCC = MAX VOUT = 0 V OE = HIGH, CP = HIGH NOTES: 1. For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at one time, nor for more than 1 second. FAST AND LS TTL DATA 4-243 MC74F299 AC ELECTRICAL CHARACTERISTICS 74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol fMAX tPLH tPHL tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay CP to Q0 or Q7 Propagation Delay CP to I/On Propagation Delay MR to Q0 or Q7 Propagation Delay MR to I/On Output Enable Time to HIGH or LOW Level Output Disable Time to HIGH or LOW Level Min 70 3.5 4.5 3.5 4.0 5.5 5.5 3.5 4.0 2.0 1.0 7.5 8.0 9.0 9.0 9.5 10 8.0 10 7.0 5.5 Max 74F TA = 0C to +70C VCC = +5.0 V 10% CL = 50 pF Min 70 3.5 4.5 3.5 4.0 5.5 5.5 3.5 4.0 2.0 1.0 8.5 8.5 10 10 10.5 10.5 9.0 11 8.0 6.5 Max Unit MHz ns ns ns ns ns ns AC SETUP REQUIREMENTS 74F TA = +25C VCC = +5.0 V CL = 50 pF Min Set-Up Time, HIGH or LOW S0 or S1 to CP Hold Time, HIGH or LOW S0 or S1 to CP Set-Up Time, HIGH or LOW I/On, DS0, DS7 to CP Hold Time, HIGH or LOW I/On, DS0, DS7 to CP CP Pulse Width, HIGH or LOW MR Pulse Width LOW Recovery Time MR to CP 6.5 6.5 0 0 3.5 3.5 0 1.0 5.0 4.5 4.5 4.0 Typ Max 74F TA = 0C to +70C VCC = +5.0 V 10% CL = 50 pF Min 7.5 7.5 0 0 4.0 4.0 0 1.0 5.0 4.5 4.5 4.0 Max Unit ns ns ns ns ns ns ns Parameter Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec FAST AND LS TTL DATA 4-244 Case 751D-03 DW Suffix 20-Pin Plastic SO-20 (WIDE) -A20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. -B1 10 P 0.25 (0.010) M B M 5. 751D 01, AND 02 OBSOLETE, NEW STANDARD 751D 03. 10 PL G R X 45 -TC K M SEATING PLANE M D 20 PL 0.25 (0.010) T B S F J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 7.40 2.35 0.35 0.50 12.95 7.60 2.65 0.49 0.90 INCHES MIN MAX 0.499 0.292 0.093 0.014 0.020 0.510 0.299 0.104 0.019 0.035 1.27 BSC 0.25 0.10 0 10.05 0.25 0.32 0.25 7 10.55 0.75 0.050 BSC 0.010 0.004 0 0.395 0.010 0.012 0.009 7 0.415 0.029 A S Case 732-03 J Suffix 20-Pin Ceramic Dual In-Line NOTES: 1. LEADS WITHIN 0.25 mm (0.010) DIA., TRUE POSITION AT SEATING PLANE, AT MAXIMUM 20 1 11 2. MATERIAL CONDITION. DIM L TO CENTER OF LEADS WHEN FORMED PARALLEL. 10 3. DIM A AND B INCLUDES MENISCUS. B A F C L N H D SEATING PLANE J M G K DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 23.88 6.60 3.81 0.38 1.40 25.15 7.49 5.08 0.56 1.65 INCHES MIN MAX 0.940 0.260 0.150 0.015 0.055 0.990 0.295 0.200 0.022 0.065 2.54 BSC 0.51 0.20 3.18 1.27 0.30 4.06 0.100 BSC 0.020 0.008 0.125 0.050 0.012 0.160 7.62 BSC 0 0.25 15 1.02 0.300 BSC 0 0.010 15 0.040 Case 738-03 N Suffix 20-Pin Plastic -A20 1 11 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEAD WHEN FORMED PARALLEL. B C L 4. DIMENSION B" DOES NOT INCLUDE MOLD FLASH. 5. 738 02 OBSOLETE, NEW STANDARD 738 03. -TSEATING PLANE K E G F D 20 PL 0.25 (0.010) M N M J 20 PL 0.25 (0.010) T A M M T B M DIM A B C D E F G J K L M N MILLIMETERS MIN MAX 25.66 6.10 3.81 0.39 27.17 6.60 4.57 0.55 INCHES MIN MAX 1.010 0.240 0.150 0.015 1.070 0.260 0.180 0.022 1.27 BSC 1.27 1.77 0.050 BSC 0.050 0.070 2.54 BSC 0.21 2.80 0.38 3.55 0.100 BSC 0.008 0.110 0.015 0.140 7.62 BSC 0 0.51 15 1.01 0.300 BSC 0 0.020 15 0.040 FAST AND LS TTL DATA 4-245 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. FAST AND LS TTL DATA 4-246 |
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